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ADE7518
IE/IEIP2 REGISTERS
IP/IEIP2 REGISTERS
PRIORITY LEVEL
PSM
IPSMF
IPSME
FPSM
(IPSMF.6)
LOW
HIGH HIGHEST
MIDNIGHT
IN/OUT
RTC
ALARM
LATCH
RESET
ADE
MIRQSTH
MIRQENH
MIRQSTM
MIRQENM
MIRQSTL
MIRQENL
MIRQSTL.7
WATCHDOG TIMEOUT
WATCHDOG
IT0
WDIR
PSM2
EXTERNAL
INTERRUPT 0
INT0
0
1
IT0
IE0
TIMER 0
TF0
IT1
PSM2
INTERRUPT
POLLING
SEQUENCE
EXTERNAL
INTERRUPT 1
INT1
0
1
IT1
IE1
TF1
TIMER 1
I 2 C/SPI
UART
TIMER 2
SPI INTERRUPT CFG.5
1
I 2 C INTERRUPT
0
RI
TI
TF2
EXF2
IN/OUT
LATCH
RESET
INDIVIDUAL
INTERRUPT
ENABLE
GLOBAL
INTERRUPT
ENABLE (EA)
Figure 75. Interrupt System Functional Block Diagram
Rev. 0 | Page 77 of 128
LEGEND
AUTOMATIC
CLEAR SIGNAL
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